Dépt. Electronique

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I am a post-doctoral researcher at Institut Mines-Télécom Atlantique (formerly Télécom Bretagne). I obtained my M. Eng. and Ph. D. degree in Computer Engineering from McGill University, respectively in 2010 and 2016.

My main research interest is the design and analysis of algorithms for hardware implementations, and particularly, novel approaches for improving energy efficiency.

I have extensive expertise in the analysis and implementation of error-correction codes (and especially LDPC codes), and telecommunication systems in general. I am also interested in neural networks, and in how they can be used to achieve energy-efficient implementations of telecommunication systems.

I have profiles on LinkedIn, ResearchGate, and Google Scholar.

Quasi-Synchronous Systems

The energy efficiency of digital systems could be improved if they could tolerate occasional circuit faults. For example, fault tolerance can be used to compensate for variations in near-threshold CMOS circuits, or more generally to reduce safety margins. 

For telecommunication and signal processing systems, a promising approach is to expose the circuit faults to the algorithms, and use either an algorithm’s natural redundancy or carefully designed additional redundancy to preserve the same quality of results when operating on faulty hardware.

The perfect example of an algorithm with redundancy is a decoder for error-correction codes, and indeed we find that letting faults occur in an LDPC decoder circuit reduces its energy consumption.

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